Field of the Invention
The present invention relates to a configuration and a method for the contacting of circuits.
Circuits and integrated circuits are contacted with a carrier material and packaged in housings for further processing.
Contacting with a carrier material is known from Published, British Patent Application GB 2 177 639 A. There, an integrated circuit is contacted with a carrier material by an ultrasonic wire bonder. The carrier material is a lead frame. Another reference for wire bonding is U.S. Pat. No. 5,395,038.
A wire bonder utilizes a long wire (what is known as an endless wire) that is located on a spool. The processing end of the endless wire is threaded through the bonding machine and led to the position to be contacted with the aid of a cannula.
In what is known as ball bonding, the processing end of the endless wire is melted by heat and ultrasound and connected to the contact pad of the integrated circuit, which is located on the integrated circuit, thereby forming a ball; hence the name ball bonding. Next, a position on the lead frame is approached with the cannula and the bonding wire inside it, and the bonding wire is joined to the lead frame. Now the bonding wire is cut, and the cannula with the bonding wire moves to the next position for forming an electrical connection.
Another method for contacting integrated circuits is what is known as wedge-wedge bonding. Here, the bonding wire is not melted by heat, but rather pressed or rubbed by a stamp on one side of the cannula.
The disadvantage of both techniques is their utilization of a bonding wire, because this is usually made of gold and is therefore expensive. Given thick bonding wires, the price of gold is the largest cost factor; for thin bonding wires, the finishing technology for creating a conformal, thin and homogenous wire is the largest cost factor.
Another disadvantage is that only one bond connection at a time in succession can be produced with wire bonding. For integrated circuits with 1,000 contacts or more, this leads to a long production time, which raises costs.
The long production time can be shortened with what is known as the flip chip technique, which is described in U.S. Pat. No. 4,887,758, for example. To accomplish this, a lead frame is utilized, whose electrical lines are disposed in such a way that they reach exactly to the electrical contact pads of the integrated circuit. The electrical lines of the lead frame are simultaneously pressed to all contact pads of the integrated circuit and connected in one process.
But the disadvantage of the flip chip technique is that only one chip can be joined with the lead frame. However, two or more individual chips are often packaged in one housing and electrically contacted. In this case, the flip chip technique is incapable of producing an electrical connection between two chips in a housing.